深圳市太航半导体有限公司

Processor ArchitectureDual-core ARM Cortex-A9 MPCore processorUp to 800MHz maximum frequencySupport for symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP)Each processor core includes:32KB of L1 instruction cache32KB of L1 data cacheNEON media processing engineSingle- or double-precision floating point unitMemory management unit (MMU)Private interval timerPrivate watchdog timer512KB of shared level 2 (L2) cacheSCU for cache coherencyAccelerator coherency port (ACP)Global timerGeneric interrupt controllerCoreSight™ instruction traceMemory Interface Support

Multiport SDRAM controller subsystem

DDR2 and DDR3LPDDR1 and LPDDR2Error correction code (ECC)Flash memory controller

NAND with direct memory access (DMA) and optional ECCQuad SPI (NOR)Secure Digital (SD)/ secure digital I/O(SDIO)/ MultiMediaCard (MMC) with DMAInterface Peripherals

Two 10/100/1000Mbps Ethernet media access controllers (EMACs) with DMATwo USB 2.0 On-The-Go (USB OTG) controllers with DMAFour I2C controllersTwo controller area networks (CAN), two master SPIs, two slave SPIs, UARTUp to 71 general-purpose I/Os (GPIOs) and 14 input-onlyOn-Chip Memory

64KB on-chip RAM64KB on-chip boot ROM

级.5AGXFB1H6F35C6N5AGXFB1H6F35C6N5AGXFB1H6F35C6N5AGXFB1H6F35C6N5AGXFB1H6F35C6N

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